HSDIO Serial Data

[QKD]

Is there a way to create a hardware shift register on the 6562 card to do a hardware compare for serial data?

and is there a way to acquire a serial bit stream of 8, 16 or 32 bits per sample?

I need to monitor a serial data frame at 1MHz and trigger an acquisition on receipt of a bit pattern indicating the start of frame. The pattern I need to detect is 0xDAAA.

I can acquire the serial data by using a sample clock of 1MHz but that is a very inefficient method as each sample is only 1 bit and I do eventually need to increase the bit rate of the serial data to 100MHz.

[Steve_B]

Hi QKD,

Our HSDIO boards are designed to perform parallel pattern matching and not serial pattern matching. If you were able to take your serial data of interest and make it parallel data using a deserializer, then we would be able to pattern match and send a trigger. The deserializer would be the hardware shift register you were asking for. You would need to be sure that the deserializer meets your requirements as far as the number of lines and the logic levels. I have included a link to a KnowledgeBase article that talks a little about the deserializer and what it does.

Extending your HSDIO Maximum Clock Rate with SerDes
http://digital.ni.com/public.nsf/allkb/8D92A482ED857CD5862572A600719F2E?OpenDocument

[Ben]

Hi QKD,

I have not used that widget myself but I have done similar, so I'll share some thoughts. 

Monitoring a serial line generally uses over-sampling of a factor of 10.

I have not looked at the spec form FASTCOM  lately but I believe it was possible to specify the sync pattern used by chip on their ESCC-PCI interface.

An close NI option would use an FPGA but I believe they top-out at 40MHz so that would only give you a X4 over-factor.

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QKD wrote:

Is there a way to create a hardware shift register on the 6562 card to do a hardware compare for serial data?

and is there a way to acquire a serial bit stream of 8, 16 or 32 bits per sample?

I need to monitor a serial data frame at 1MHz and trigger an acquisition on receipt of a bit pattern indicating the start of frame. The pattern I need to detect is 0xDAAA.

I can acquire the serial data by using a sample clock of 1MHz but that is a very inefficient method as each sample is only 1 bit and I do eventually need to increase the bit rate of the serial data to 100MHz.

---

So for an over-sample of X10 you would need to acquire at 1GHz. This exceeds the speed of PCI based machines so you would have to use an PCI with a faster backplane. You could acquire using a scope board and then process the data after the fact.

If you have to to it as its happening, then you could "divide and conquer" by syncronizing multiple PXI chassis, such that the each take on part of the work and the results are merged.

I am sure this is not the reply you were hoping for!

Ben

[Ben]

This thought crossed my mind...

Instead of over-sampling serially (one after the other) over-sample in parallel by driving multiple DIO lines wit the same signal. Each DIO line "votes" high or low and the majority wins. That would reduce the bandwidth required at the top end of your spec.

Ben

[JuanCarlos]

QKD,

Do you have an incoming clock  with your serial data? If so, I would recommend to set your device to a "data width" of 1 byte to optimize data packing and sample the data with an immediat trigger. Once the data is acquired, use software to deserialize the data and look for your sync pattern. Do you know if the sync pattern is unique no matter what the bit alignment is in the serial stream?

This may sound like software overkill, but typically the board has enough on-board memory to make this possible and save you any extra hardware. 

I hope helps,

Juan Carlos