Has anyone done boundry scans using LabVIEW?

[FK55]

I am new to the world of FPGAs and boundry scans. My experience is with RF. My current project deals with trying to check Logic levels
on an FPGA. I have checked into the JTAG Technology for there test unit and code. Are there any others? It ia an Altera device.

[AllanS]

Hello FK55!

Are you using FPGAs to perform the boundry scans or are you performing boundry scans on the FPGA? We have a product called TestStand that has some JTAG technology integrated into it. Are you asking what technologies beyond JTAG is used to perform boundry scans? Let me know and have a great day!

Allan S.
National Instruments

[FK55]

I am doing boundry scans on an Altera FPGA. Currently they are using a DMM to check the logic levels. This has disaster written all over it. I have looked at the PXI hardware and Acculogics PXI hardware. What version of TestStand are you using? I have a limited experience with 3.0

[AllanS]

Hello!

What type of DMMs are you using? Optimally how would you like this done? Let me know some more details and I will do whatever possible to help you out!

In TestStand 3.0 and beyond there are JTAG addons. I have attached a link to this below.
http://zone.ni.com/devzone/conceptd.nsf/webmain/2662f87d4d09111e86256fff00832a12

Have a great day!!

Allan S.
National Instruments

[FK55]

It is a hand held Fluke. The points is very sharp so that it can touch each of the test points. This also allow the operator if they miss the test point to scratch the PCB. There is a 10 pin header on the PCB to program the FPGA. I would like to use that header to verify the logic highs and lows or voltages which ever will work. In LabVIEW I can determine if it is a High or Low.