Hi
I have deloped a .vi which is deployed over FPGA.
The VI is having one while loop and inside the while loop I am accessing CAN9853 module(FPGA IO).
I am sending one CAN frame to this module for each iteration of the loop.
When I run that VI (Interectively) I can see all CAN message over BUS monitor(USB to CAN connected to 9853(CAN0)).
The problem is we are not able to see more than 2 CAN frame when the FPGA vi is made as run as startup.
Kindly help.. Is there any settings need to be done.
