High Performance Timed Loop on NI RT Target

[pegahm]

I am executing a timed loop with essentially no code in it and the timed loop is running off of a 1MHz clock on myRIO 1900 NI Linux RT. Timed loop period is set to 1uS; however, the fastest iteration duration is measured to be capped at 10uS. I was wondering if there is actually a cap on the iteration time of the timed loop on RT or my approach on measuring the execution time of the timed loop is wrong. 

[GerdW]

Hi pegahm,

I was wondering if there is actually a cap on the iteration time of the timed loop

Sure: CPU speed!

When you want to achieve loop iteration rates of >2kHz (with little jitter) you need to employ the FPGA of your myRIO…

[pegahm]

Hi GerdW,

But I have been able to achieve almost 100kHz on this RT (close to 10uS loop execution time) on the same target. My application is complex and could not be implemented on FPGA solely. 

The CPU of myRIO is 667MHz and I am wondering why does it take almost 6000 clock cycles to execute such simple code in my timed loop.

Do I need a more power RT target if I want to achieve 1uS on RT?

Also, I was wondering if there is a documentation from NI that would provide my detail information on what is happening in the background?

Best,

Pegah

[crossrulz]

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@pegahm wrote:

The CPU of myRIO is 667MHz and I am wondering why does it take almost 6000 clock cycles to execute such simple code in my timed loop.

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In your example code, you are running into issues with memory allocation slowing things down (the autoindex output tunnel of a while loop causes memory to be allocated each iteration).  Try preallocating the array and use Replace Array Subset with a shift register and see if your times improve.

[pegahm]

I did remove the indexing but that didnt help either. I have attached the most recent work.

[crossrulz]

The other thing I would add would be to set the CPU affinity.  This avoids cache having to be moved around between cores in the CPU.  I am not expecting that to help much.

[pegahm]

Yes, I have tried this before but that didnt help much as you predicted.

[JensG69]

Perhaps the reason for the "slow" execution is that you run this code interactively. Have you tried to build an exe? And in that case, evaluate the performance of the timed loop not directly after startup of the rtexe.

Regards, Jens

[pegahm]

Hi Jens,

Yes,  I have tried that as well. Running the code as RT Application and log the execution times on a file. However, I got the same values for my execution time.

My only guess at this point is that there might be overhead added due to the Timed Loop itself. 

Best, 
Pegah

[alyssa.h]

pegahm,

If you take a look at the document below, you will see that the cRIO-90xx can't run a Timed Loop at 1MHz, and a myRIO is less powerful.

Timing Sources Available for LabVIEW Timed Loop by Platform

If you need to run something that quickly, I would suggest doing just that part on the FPGA of the myRIO and then the rest of your code on the Real-Time OS. The FPGA will also allow you to do Single Cycle Timed Loops.

Single-Cycle Timed Loop FAQ for the LabVIEW FPGA Module

Regards,

Alyssa H.

National Instruments