Basically, I have this one case structure in my single cycle timed loop on a 40 MHz FPGA target and this one structure keeps causing the theoretical maximum clock frequency to be less than the desired clock frequency. If I use a disable diagram structure around this thing, the code runs, so I know it's this specific part of the VI. I guess my question deals with how I can reduce "combinatorial paths" and propagation delays in this case structure. Could I replace the case structure with something else, achieve the same results, and fit everything in an SCTL effectively?? I know seeing the files will help big time, so I'll upload them ASAP. In the mean time, any tips and tricks are greatly appreciated. Thanks!
