How can i control iteration in host side?

[auree123]

Hi,

Please see the attachment.

My intention is to control the loop rate in host side in order to make the no. of iterations user specified by input time.

By the block diagram that I implemented, I can control the iteration only at sampling rate 1000 samples/second. If I increase the sampling rate, it takes longer and if I reduce the sampling rate, it takes smaller time than the specified before program stops. Can anybody tell me what wrong with my logic?

The loop rate at FPGA side is in microsecond and the same at host side.

Any recommendation would be appreciated.

[MorganS]

Hi auree123,

I'm not sure exactly what the problem is from your description - could you explain more about the behavior you're seeing?  One thing I noticed: you have controls for Sampling Rate (in samples/second, I assume) and for Time to Acquire Data (in seconds?).  The output of that multiplication will give you the number of samples - perhaps that value is what you meant to compare with the iteration terminal to decide when to stop the loop?

Thanks,

Morgan S

Applications Engineer

National Instruments

[auree123]

Yes, I like to stop that while loop after acquiring that much samples.

Could you please recommend me what should I do additionally or what's wrong with my current design? Or, any alternative way to stop data acquisition from host side? I tried using wait functions in FPGA, it didn't work though.

Any suggestions would be appreciated.

[MorganS]

Hi auree123,

I'm still not 100% clear on what you need this VI to do.  Could you provide some more detail about the problem?  If my assumptions about the Sampling Rate and Time to Acquire Data controls were correct and you simply want to stop the while loop at that point, try somthing like this:

Thanks,

Morgan S

Applications Engineer

National Instruments