How do buffered period measurements work?

[deserio@florida]

How does the Measure Buffered Period (DAQ-STC).vi work? Are there interrupts triggered by the gate signal to make the CPU take a reading and save it, or is the gate polled to determine when to read the counter contents? With my PCI-MIO-16E-4, on a P166 PC, the vi seems to miss many measurements, (though those it does make are correct) while the Meas Buffered Pulse-Period (DAQ-STC).vi seems to works just fine (reads correctly except for the first period, and none are missed). This latter program looks nearly identical to the former, but uses older compatibility vi's to do the job. Does anyone know why the newer vi might have problems that the older one doesn't?

[Raecine Meza]

Although the counter functions are identical
for both examples, remember that the first DAQ vi each calls sets the counter for a specific counter operation. Buffered Period measurement has a different timing diagram than Buffered Pulse measurement.
Buffered Pulse-Width measurement counts between the rising and falling edge of the gate signal's active state while Buffered Period Measurement counts from one active edge to another.

You can find the timing diagrams for counter operations in the user manual of our counter/timer boards. Although this is not the user manual for your particular board, the timing diagrams given for buffered period and pulse measurement are still applicable. Check out http://www.ni.com/manuals to download the PCI-6602 manual and skim th
rough Chapter 3.

[deserio@florida]

Thanks for the suggestion to read the manual. (Always a good idea.) Both of the vi's I mentioned have controls as to what is to be measured. Both can measure the period between the edges of the gate. My question is how the HW save register is determined to have a valid reading. The manual says this HW register is latched on the appropriate gate transition for a software read. Is there an interrupt generated to tell the software to do the read or does the software have to figure it out some other way. My gate signal is 0.5 ms long. If the software has to see the gate transition, and the gate is short (mine are 0.5 ms), might there be missed periods?