How does "total amount of requested elements" correspond to Block RAM?

[Ohitstarik]

We're running a cRio 9112, and acquiring data from an NI 9853. 

I'm trying to get this labview project to run that a previous intern had left over, and my labview knowledge is pretty limited. 

The program is supposed to acquire data from an RPM sensor. It compiles fine, but doesnt actually show any data. I've already checked the hardware, but I'm planning on checking wire continuity to see if theres a break/disconnect anywhere if I can't get the settings right.

Currently, the previous intern had set it to request 32k elements (this is all edited through the Mod1_fifo_to_pc properties page). The previous intern told me to try upping that and that might help get data. When I try that, it tells me that the file is too large for the FPGA. 

The Error message i get is:

ERROR: Pack:2310 - Too many comps of type "RAMB36_EXP" found to fit this device. 

ERROR:MAP:237 - The design is too large to fit device. Please check the Design summary section etc etc

This only happens when I up the requested elements up from 32k to 65k. So i'm guessing that it means that i'm requesting too many elements?

Further research showed me that I didnt have enough space to transfer the data. From the cRio 9112's manual I see that I only have 1152 kbit/s of block ram

The question:

How do I know how much total elements I can request from the NI 9853? how much "data" is one element? I don't have any fundamentals here so reading material (if you guys know of any about this topic off the top of your head) would be great as well.

[GerdW]

Hi Ohit,

We're running a cRio 9112, and acquiring data from an NI 9853. 

The NI9853 is a CAN module. There is no CAN-related stuff found in your VIs…

There are just some AI channels used on your FPGA VI. Unfortunately you didn't attach the whole project so we cannot see what kind of modules you use in your target. We also cannot examine the settings of the FIFOs, as that information is also only available in the project file!

[Ohitstarik]

Sorry, just figured out how to attach folders.

The VI contains stuff to gather data from ALL of our sensors. that includes load cells, current sensors, etc. those will be useful later on but i'm trying to get the RPM sensor to start working first. It went into Analog intput 7 which lines up to NI9853

[bseguin]

The size of the FPGA and the size of the memory are both a critical factor that are not 100% related. It's all depend on the software you develop.

Since it's a FPGA and the CRIO is connected directly to it, you can download more often the data in a FIFO that the CRIO will use later. You always have to reduce your code and memory size used in a FPGA. if not, you will reach quickly the limit of it.

Benoit

[GerdW · Accepted solution]

Hi,

The VI contains stuff to gather data from ALL of our sensors. that includes load cells, current sensors, etc. those will be useful later on but i'm trying to get the RPM sensor to start working first.

Your FPGA VI is

• reading signals from Mod1/AI0-7 and Mod2/AI0-3
• trying to determine a RPM value from Mod1/AI7 signal
• those data are queued into 2 FIFOs

I STRONGLY recommend to replace the stacked sequences used to put stuff into the FIFOs by FOR loops: now you only need one instance of the FIFO node for each of the FIFOs (instead of 12 instances right now!)

Did I emphasize that STRONGLY enough?

It went into Analog intput 7 which lines up to NI9853

No. AI7 is read from Mod1 as can be read in the FPGA IO node.

There is NO CAN communication in your FPGA VI…

[Ohitstarik]

This is good advice. I'm going to read up and make those changes. So the error i'm getting isnt based on the requested elements, but it's a symptom of a bigger problem which is the amount of stuff I have in the program that could be a lot less.