How to Simulate Host to Target DMA FIFO?

[a1650078]

I am trying to debug some FPGA vi's which use external IP's based on AXIS. I have been trying to test them using desktop execution node in one loop while I write and read from DMA FIFO's in the other. The writes simply never happen, and the sampling probes show that the Read FIFO method on the FPGA never asserts 'Output Valid'. Could some please point me in the direction of an example that combines Desktop Execution Node with a host to target DMA write? The example in LabVIEW FPGA only passes data target to host.

[MaxJoseph]

I might be misunderstanding; the desktop execution node simulates the operation of the FPGA.vi in one loop and you are trying to write into Host-To-Target DMA FIFOs in a parallel loops. The simulated FPGA.vi FIFO reads never assert that they have received a valid data? I am not so familiar with desktop execution node, would you expect to be able to access the simulated resource through the FIFO writes?

I suspect that this is not the case. I thought DEN was for simulating FPGA logic, rather than simulating architecture level communication between loops, particularly loops running on different hardware. In my development I make little wrappers to test these sorts of components. I would feed in dummy data and have the FPGA.vi simply read the data and pass it back to the host, which I can then review for accuracy.

[a1650078]

Yes, according to the documentation the DEN has supported DMA FIFOs for several years. In fact, after fixing a few bugs in my handshaking code, the simulation did indeed work as expected. I was not so lucky using the IMAQ FPGA Image Transfer to Target, which crashes the simulator with an internal error in LabVIEW 2017 on Windows 10, but the support for simulating DMA seems pretty solid otherwise.