How to configure a dummy write function for target-scoped FIFO?

[stevensung]

I am working on a project to build a cRIO server. In order to minimize actual amount of coding I decide to borrow from an existing project that one of my colleagues developed before.

The only major difference from my project is an NI9871 module that handles RS485 communication. For that to work I have to configure it to RIO scan mode in the chassis. Thus it takes two of three available DMA channels. The project I took from my colleage has already two DMA type FIFOs defined, which means I have to at least change one of them from DMA to something else. The easiest approach is to change it to a target-scoped FIFO so that the coding of the rest of the project does not has to be modified, especially that of the host application. However, I then realized only a read function of this FIFO is used in the FPGA, which definitely triggers a complilation error since a corresponding write function of this FIFO can not be found i the same block.

OK. Here is my question:

How do I configure a dummy write function for this target-scoped FIFO?

According to the design my FPGA vi only calls the Read function to continuously read data from host application through this FIFO. The host application is responsible to write required data to it in order for FPGA application to retrieve. So if I have to present a dummy write function, it should not write anything to the FIFO. Otherwise the content in the buffer will get messed up and readout from it will become garbage.

Could anyone give me advice on how to configure this? Thank you.

[nathand]

I think you're missing a critical piece of information.  DMA FIFOs are used to transfer data between the host and the FPGA.  Target-scoped FIFOs are used to transfer data between loops in the FPGA.  You can't simply swap one for the other.  The DMA FIFO write from the host will no longer work if you change the DMA FIFO to a target-scoped FIFO.  Unfortunately, a dummy FIFO write won't solve your problem; you need to rework your code.

[stevensung]

Yes I know DMA is the only type of FIFO that can do data transfer between host and FPGA.

The challenge I have is to build a system that has one NI9871 module and capability to perform data transfer between host and FPGA in two separate channels.

As I mentioned before setting up NI9871 in RIO scan mode will take two of three available DMA channels that FPGA chip has. Therefore I have to leave one of my two

data transfer between host and FPGA in DMA and change the other one to something else.

This something else thus gives my headache.

All I want for this data transfer is through a FIFO like buffer structure that can be accessed from both host and FPGA ends. If I do that via normal UDP data package way

then the coding will be a lot and efficiency will not be as good as I want.

Is there a better approach to realize that in FPGA?

Thank you for your further input.

[nathand]

The only alternatives for passing data between the FPGA and the host are 1) DMA FIFOs or 2) front-panel controls.  I'm not sure why you mention UDP since it is not an option for communicating with the FPGA.

Front panel controls are not as efficient as FIFOs for transferring large amounts of data.  However, since you have run out of DMA channels, you could create a similar scheme using front panel controls and a target-scoped FIFO.  On the FPGA you'll need to add an extra loop, containing two front-panel controls: a data value (of whatever type the FIFO would have been), and a boolean for handshaking.  Whenever the handshaking boolean is true, read the data value, write it to the target-scoped FIFO, and set the handshaking boolean to false.  On the host side, you'll wait until the handshaking boolean is false, write a new data value, then set the handshaking boolean to true, which will trigger the FPGA to read it.

I have not used the 9871 module, but it is probably possible to control it from your code rather than using scan mode.  This requires more FPGA coding but gives your more freedom in the use of DMA FIFOs.

[stevensung]

Your first option seems quite promising and I am actually implementing it.

Hopefully that will solve my problem.

Thank you for your help.