How to efficiently histogram in cRIO

[Chatwin]

The attached file describes how I think one would efficiently build a histogram of a clocked digital bus using cRIO FPGA.  It takes the bus value as an index into an array of byte-sized counters, adds one, and puts it back; the value is checked for overflow and if any counter is maxed out then the array will be buffered out to the controller.

Trouble is, this compiles for 4.5 hours, and then "failed to compile."  How do I make this simple concept even less complicated?

[jareds]

Hi Chatwin,

How is the compile failing?  Is it timing, space, etc.?

Also, you should try to avoid using controls and indicators to pass data as much as possible, especially with arrays.  You should look at having a parallel loop pass the data up to the controller.  In order to do this, memory structures such as look up tables would need to be used to store the histogram and pass it from one loop to another.