How to integrate a FIR filter created with the IP generator in my Processing WHile Loop??

[flote]

Hi!!

I'm having a lot of problem to integrate the DFD FIR filter in my TOP(FPGA). VI. I want to replace the FIR Filter for this one. But it's not possible because the DFD Filter is bouilding under a Timed Loop and it's no possible to put a timed loop inside a whiel LOOP. Hava a LOOK to the project attached.

Thanks

[iZACHdx]

I'm not exactly sure what the problem you're having is after reading your description. It is very possible to place a timed loop within a while loop in a FPGA VI. Perhaps you are getting this confused with the opposite implementation. You would be correct to state that it is not possible to put a while loop in a timed loop. From what I see of your FIR_LP filter VI, the way you are exchanging data is with FIFOs. You are doing the same thing in your regular processing loop except the FIFOs are different ones. Based on that, you need to exchange information from your FIFO in the normal while loop to your FIR_LPDataIn FIFO and then read it back out from the FIR_LPDataOut so that you can pass it to the FPGA-HOST2 FIFO. There are a number of ways to do this and the picture below is just one way to do things. One thing to keep in mind with your current architecture is that the one thing currently hindering the placement of the filter VI within the while loop is within the FIR_LP filter VI itself. This is because you it is set as an infinite timed loop - which means that even if you place it within the normal while loop, you will never proceed to the next iteration of your outer loop. To get around that, you would need some way to get the timed loop to stop. In the context help for the filter core, it shows that it requires two cycles per sample so you know that you couldn't just change the boolean constant to a true. I would imagine that if you tied the Output Valid output in the filter core subVI to your conditional terminal, it would operate as expected if placed within the regular while loop and if you properly sequence the FIFOs. You could also simply take the code for the filter and place it somewhere in the FPGA top level VI as I did below.  Also, don't forget that you can use the option to execute your FPGA VI on the development computer to help troubleshoot things. \

**Note that I left your data types intact - since you are converting between fixed pointed and a signed integer value, you could be losing some data and you may need to change the data type of your FIFOs if that is not intended.