How to minimise myRIO FPGA resource usage?

[a1650078]

When I try to compile an empty myRIO FPGA vi, the compilation process reports high resource usage and takes longer to synthesise than I would expect. I understand that the LabVIEW adds some overhead for control/indicator communication but 47.6% seems like too much. Is there any way to reduce it?

Thanks

[Terry_ALE]

More generally, utilization isn't linear and the FPGA compile tools 'try harder' the more logic is placed.  Do you think you will run out of room when adding your design?

Did you check the compile options under the build specification?

[a1650078]

Yes LUT usage is a limiting factor for the performance of my design. I can get by with less, but I'm wondering if there's any functionality I can disable. The FPGA is being used for image processing only, so there is no need for I/O or controls/indicators. The compilation settings make virtually no difference. Is this the expected overhead for a completely empty vi?

[Terry_ALE]

I suggest you code up the design to see how the tools handle it.

[DanielRoth]

Hi - are there some ideas and solved issues about it?

[rolfk]

There is not much you can do about that. The myRIO and other ARM based RIO hardware is using the Xilinx Zync7000 series chip. There is no seperate CPU on these systems but part of the FPGA fabric is used to build this ARM CPU. That and the necessary interface logic to the rest of the various systems including IO, takes up a significant part of the FPGA fabric. The problem is extra large on the myRIO since it uses the smallest Zync7010 chip available. Some cRIO's have a bigger Zinc7020 chip which has more FPGA resources.