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How to optimize the FPGA vi in 40Mhz clock?

Hi

I am using LabVIEW 7.0 and LabVIEW FPGA 1.0. I was trying to simulate the serial read/write implementation example and i am not able to successfully compile the code for read implementation at 40 MHz where the data bits is 32 and baudrate 100KHz. But i am successfully able to do write implementation at the same baud rate using the 40 MHz. Can somebody help me to use optimizing techniques to do this? Or is there any other way to achieve this?


Thank you
Subramania Bharathi
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Please see the following link.

Regards,

Kristi H
National Instruments
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