How to pass FPGA DI pins from FPGA implemented vi to RT impemeted vi

[SASA1]

Hello,

   I'm using two "FPGA sbrio"  DI to implement RS232 data protocol (RX, TX)

   I'm able today to communicate with 1 deveice with this protocole.

   i want to communicate with 3 device (in parallel) from the FPGA throught this code (RS232).

   the pins are coded inside the FPGA main RS232 main code,

   i have three RT vi to communicate with 3 different devices using this code), but now i want to communicate with them simultanouly. so how can i configure the FPGA pins throught

  so i need in each vi to specify the DI pins to communicate with via rs232, how i can do this?

   Regards,

SASA

[crossrulz · Accepted solution]

Your architecture will need to change a lot in order to do this properly.  You should read the data through a FIFO instead of using the front panel interface.

I recommend changing your VI so that it is a subVI.  Make sure it is reentrant.  For inputs, you will want your pins and a FIFO reference.  Then in your main VI, you just call this VI three times with different constants to the inputs to designate different pins to be used.  Use a DMA FIFO to read the data that is to be sent with some extra data to tell you which bus to send it to.  You then just pass the data along via whichever FIFO belongs to the port your are writing to.

[nathand]

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@crossrulz wrote:

Your architecture will need to change a lot in order to do this properly.  You should read the data through a FIFO instead of using the front panel interface.

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I don't see any problem with just duplicating the existing code several times, and labeling the front-panel controls differently. If the RS232 is fairly low-speed data and not continuous communication, and if there's enough space on the FPGA, then continuing to use front panel items should be fine. Save the DMA FIFOs for high-throughput data.

[SASA1]

Thanks to all, the second solution seems to be more seweetable, but  i cannot compile 3 FPGA main in one single board,  then how to pass FPGA reference in the RT

[P@Anand]

If you have 3 different VIs call them in a single VI and execute it, then your compilation will be once. In RT you have the "Open FPGA VI Refernce" function to do this. Just Right Click and go to Configure Open FPGA Reference VI and select the option you want. When you pass this reference to the FPGA Read/Write control node you will be able to see the Controls/Indicators available in the FPGA VI. Unless you don't have any requirement not to loose any data I would suggest the same nathand suggested.