How to reduce LabVIEW FPGA signal generation frequency error

[vnetawz]

When I generate sine signal using Sine IP on FPGA by CRIO 9038, I found the actual frequency is always 2.5% smaller or larger than the set value, no matter low frequency or high. And the signal data obtained from FPGA verifys this. So I wonder why this happen because there seems nothing I can do to enhance this. The Normalize signal  generation parameter convertor VI runs on the computer, so it has nothing to do with FPGA setting.  Is such error the property of FPGA? Or the LabVIEW?

[GerdW]

Hi vne,

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@vnetawz wrote:

When I generate sine signal using Sine IP on FPGA by CRIO 9038, I found the actual frequency is always 2.5% smaller or larger than the set value, no matter low frequency or high. 

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The numbers on your image only differ 0.35% / 0.024% from expected value...

How is the code shown in your image related to FPGA? I guess that code runs on your RT target?

[BertMcMahan]

The point of that VI is to convert into fixed point data for periods per tick. What is your FPGA clock rate input? What do the fixed point outputs show?

[vnetawz]

Thank you for reply and correction. Sorry, I may have the wrong conclusion. But for low frequency, like 0.1Hz, it does result in about 2.5% error. And it get better when frequency increases as you found. The FPGA reference interface runs on PC.

Regards!

[vnetawz]

Thank  you BertMcMahan!  The help doc says output fixed point variables are “unsigned fixed-point data type with a 32-bit word length and a 0-bit integer word length”. I didn’t monitor them and sorry now I have no access to my device. 

But I am afraid even if they are monitored it may make no sense, since the output signal is right the frequency of the displayed one. So I am more concerned of the converter itself.  

Regards!

[vnetawz]

Hi  GerdW  and BertMcMahan, thanks for your direction. I think I may have found the reason. The converter VI program is as below which I forgot to double click to see how it works before. The actual frequency is calculated by dividing desired frequency by 40M (FPGA clock) and then converting it to a 32 bits FixedPoint data type. The quantization of FXP(32,0) is 2^(-32)=2.328E-10. So we can calculated the minimum desired frequency  quantization by solving f/40M=2^(-32), f=0.009312. Because of quantization, when desired frequency f_d is assigned, f_d needs to be converted to the nearest FXP(32,0), thus the error. And the small the frequency, the larger the error.

[vnetawz]

Thanks BertMcMahan and GerdW for your kind help!

The VI program may tell everything. The error comes from the quantization of FXP<32,0> which is 2(-32)=2.328e-10. And the frequency converted to FXP is calculated by f_d/40M, so the minimum f_d is 0.009312. Because of the quantization, the smaller the f_d is,  the larger the error will be.