How to set VHDL Generic data type value when using the CLIP ?

[CyGa]

Hi!

I want to use the CLIP functionnality to reuse my VHDL IPs. Nevertheless, in one of my IP I have a generic to set. How can I do that ?

[RyanB]

The CLIP does not yet support IP with generic inputs.  The best solution today is to create a VHDL wrapper around your IP to set the generic value.  A few questions about your application:

What are the generics used for in the IP?  To configure port widths on the IP?  Or to configure internal logic?

What data type is this generic?

Thanks,

RB

[CyGa]

Dear Ryan,

In the code I'm trying to use, the generic is used for port width...

Here is its declaration :

generic(

        ss_number        : POSITIVE  range 1 to 32

        );

and its use :

reg_slaveselect_i       : in  std_logic_vector(ss_number-1 downto 0); 

[CyGa]

Dear Ryan,

Maybe you can help me on another point. The IP i'm trying to convert from VHDL code to CLIP node is using a custom made library (library work; use work.my_pkg.all ). When trying to compile my LV code, it generates an error because the library cannot be found. Is there a place where I should my library so it is recognized by the compiler ?

[RyanB]

Make sure the VHDL file containing your library (my_pkg.vhd) is declared in your CLIP XML implementation list (all source files must be included in this list).  This will tell LabVIEW to copy this file to the compilation directory, and allow the Xilinx compiler to find the library.  Example:

   <ImplementationList>
    <Path>..\ClipTop.vhd</Path>
    <Path>..\ClipCore.vhd</Path>

    <Path>..\My_Pkg.vhd</Path>

  </ImplementationList>