07-30-2007 12:49 AM
07-30-2007 12:58 AM
07-30-2007 02:09 AM
07-30-2007 08:12 AM
Hi,
The method that I would use would be to have a loop that acquires from the analog inputs and then immediately sends the data to a DMA FIFO on the FPGA side. Since this loop is on FPGA, you do not need to add a wait to the loop. The read function from that cRIO analog input module will clock your loop.
Good luck,
Mike
07-30-2007 09:18 AM
07-30-2007 08:13 PM
07-31-2007 01:17 AM