How to transfer array data using FIFO in LABVIEW FPGA timing loop?

[ddddd212]

Hello everyone, I'm currently facing a tricky problem. I'm using myRIO to read the time-domain data from my 20 microphones, but I don't know how to use FIFO to transfer the array data to the host computer. I tried using a for loop, but it can't be used inside a timed loop. So, what should I do? Thanks!

By the way, the state machine approach in my screenshot isn't feasible because it would alter my sampling rate.

[GerdW]

Hi dd,

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@ddddd212 wrote:

By the way, the state machine approach in my screenshot isn't feasible because it would alter my sampling rate.

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What is the sample rate?

What about writing the mic sample data array to a (memory) buffer, then transfer the buffer data to the FIFO in a different loop?

[ddddd212]

Hello! GerdW, my microphone sampling rate is 48kHz. The screenshot below shows the code changes I made based on your answer. Could you please check if I did it correctly? Also, I have another question: if data is transmitted this way, it is highly likely that duplicate data will be transmitted because I don't know how to connect my FIFO Input Valid. Thank you again!

[GerdW]

Hi dd,

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@ddddd212 wrote:

my microphone sampling rate is 48kHz.

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So you need to transfer data at 48kHz * 20 mics * 16bits/sample ~= 2MB/s?

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@ddddd212 wrote:

The screenshot below shows the code changes I made based on your answer.

Could you please check if I did it correctly?

Also, I have another question: if data is transmitted this way, it is highly likely that duplicate data will be transmitted because I don't know how to connect my FIFO Input Valid.

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I would add one more entry to the memory buffer to be used as a flag (or counter). The producer (DAQ) loop sets this value, the consumer (FIFO) loop reads the value. The other data of the the buffer is only send to the FIFO when that flag has changed to indicate new samples. Then you can set the FIFO "input valid" to TRUE.

What do you do with memory address 0?

[ZYOng · Accepted solution]

Target-scope DMA FIFO can run in SCTL. Use it as a buffer to transfer data out of the SCTL then stream the data to host using Target-to-Host DMA FIFO.

See Transferring Data between Devices or Structures Using FIFOs

[ddddd212]

Thank you all for your suggestions. I have now resolved the issue. Please refer to the screenshot below for details. Thanks again!

[Terry_ALE]

Make sure to connect the Timeout? boolean outputs to latched boolean indicators.  A timeout means data is being lost.

Since you are in an SCTL, I recommend changing to Handshaking interfacing, see https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/choosing-between-the-fifo-interface-op...