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How to use k type thermocouple in FPGA

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I'm using NI USB-7855R(FPGA) device.

I would like to acquire a temperature for k type thermocouple through AI channel 0 (terminal block SCB-68A).

But

I'm not sure how to configure it.

If someone has information for a coding procedure or an example code or a related site

can you let me know that?

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Accepted by topic author dream4me

I haven't used that device before but a quick read of the specifications suggests it is not the right device to read a thermocouple directly.

 

https://www.ni.com/pdf/manuals/374241a.pdf

 

It looks like the smallest range you can set the AI channels is ±1V and it has an accuracy in the order of ±250uV. 

 

This image shows you approx thermocouple voltages at different temperatures and you can see that they aren't miles away from the magnitude of your accuracy. In other words, whilst you might be able to measure the thermocouple voltage directly, it won't be overly accurate.

 

https://en.wikipedia.org/wiki/Thermocouple#/media/File:Intermediate_temperature_thermocouples_refere...

 

I would suggest buying a thermocouple signal conditioning unit. Depending upon what you buy they will amplify (and probably linearize) the thermocouple voltage to 0-10V or something similar. You can then wire this to your USB device to measure the voltage and scale it to temperature.

 

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thanks for your kind answer.

I think that it would be better to buy an amp. for thermocouple without wasting time.

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In the past I've also used an R Series Expansion card for C Series Modules.  This can be plugged into an FPGA card into one of the all digital connectors, and gives a 4 slot chassis that can have devices plugged in.  From there you should be able to plug in a thermocouple card and read it.  It has been several years since I used one of these but at the time it was for adding CAN ports and current readings to the FPGA card.  But yeah a much cheaper solution would be to use something from Analog Devices, or Omega that converts a thermocouple to a 0-10V reading that the FPGA can read.

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