I need advices about FPGA

[JulieStrath]

Hi

Here is my "problem": I have to hurry to finish a project where I have to configurate a compactRIO with real-time controller, NI9870, 9211 and 9215. I would like to collect the data each second from the instrumentation and store everything in an Excel file. It will be a long term experiment. I am completely lost in all the tutorials/examples/solutions proposed and I don't know what to use!

Here are some of my questions (to show how lost I am):

- what is better: FPGA project or a Real Time one?

- do I have to use TDMS?

- will I have to use FIFO?

- what is the difference between the use of a loop timer in a flat sequence loop (for FPGA) and a time loop using the onboard clock?

If you could just help me before I sank completely...

Best regards,

Julie

[Hillman]

Hi Julie,

When using the cRIO, you have to delevop two vis, one to run on the FPGA - which normally handles inputs/outputs and one to run on the cRIO - which processes data, and then sometimes a windows host vi to log the data, where you may want to do the file saving.

In the example finder, help>>example finder>>Hardware Input and Output>>cRIO>>Basic IO>>Analog IO --looks like what you'll need.

You could use FIFOs if it was important that your FPGA, RT processor and Windows PC were synchronous. I think you should use FIFOs be ause if the fpga loop has a smaller loop time than the RT controller, the RT controller cannnot communicate all the data to the windows host, thus not all of the data will be written to file, and some of the data will be lost. A useful starting point.

TDMS is binary file type for NI products. You dont have to use it. Have a look at the express vis for writing to files - if your just prototyping. Or the spreadsheet file.vi should be able to be opened by excel also.

And for your last point - why are you asking about timing loops etc?

Regards,

[JulieStrath]

Hi

Thanks for your answers, it's a bit clearer. I ask this question about the timing loops because when I went to the seminar about Embedded Design, we used the onboard clock via a timed loop. I wanted to know the difference with the solution proposed in the examples (flat structure in while loop).

One more question: to write to an .xls file: do I do a different VI? Does it have to be with the host or with the fpga?

Regards

Julie

[Hillman]

Hi Julie.

Good question.

With FPGAs you normally use as many loops as possible, as they can do millions of events in parallel thus the overall time the vi takes to run or iterate is significantly reduced. FPGAs would also use the onboard clock for all operations. Depending on the code, for example, using interrupts a flat sequence structure can be used in FPGAs to handle events, due to this parallel operations can cause issues. Whereas in labview, normally the use of sequence structures are discouraged because users should understand the concept of data flow within labview. Another useful (depending on your application) aspect of timed sequence structures is that the 2nd frame, can be timed also, but you can generate an indicator to say the first frame finished late etc So you can more control of the events that have happened and when. I hope this has cleared things up a little more.

With the xls file writing, you should do this on your host, depending on your rate I would do it on the windows host computer, and send the data from the RT host (cRIO) in chunks. I would use the 'write to spreadsheet.vi' because this creates a comma delimited text file which can be read by excel.

Please response if you have any more questions / maybe include more details on  your application.

Regards,

[Wiebe@CARYA]

Julie,

"JulieStrath" <x@no.email> wrote in message
news:1219065005448-763401@exchange.ni.com...
> what is better: FPGA project or a Real Time one?-

That doesn't really matter. You could also create an empty project, and add
a RT target and FPGA target yourself.

I'd create a FPGA project. This will give you the opportunity to add a RT
target as well (use CompactRIO Reconfigurable Embedded System).

If you choose RT system, you get a template for communication as well. This
might work for you, but I like to make my own decisions.

>do I have to use TDMS?

Of course not. TDMS is just a format to save your data in. You can also use
any proprietary binary or ASCI format. But TDMS has a lot to offer.

> will I have to use FIFO?

No. A FIFO is one way to send data to (or from) the host. You can also use
controls. FP controls on the FPGA are accessible on the host.

But a FIFO is a good choice if you have to send data to the host every now
and then.

> what is the difference between the use of a loop timer in a flat sequence
loop (for FPGA) and a time loop using the onboard clock

Not much. But a while loop loops until you tell it to stop. A flat sequence
will only execute once, unless you put a loop around it.

>If you could just help me before I sank completely...Best regards,Julie

Hope this helped a bit. Don't hesitate to ask more questions.

Wiebe.

[JulieStrath]

Wiebe, Hillman, thanks for your answers. I'm going to try all that stuff and I'll contact you if I have other questions.

Regards,

Julie