I need any IN LAB View FPGA Engineer,I'm tired of searching

[mangood]

Dear
I have work on vhdl language for more than 2 year on xilinx FPGA using  xilinx ISE

I now work on labview FPGA due to its fast programming

I have main  problem  with LABVIEW FPGA and not solved until know which it as follow

when I need to build system in FPGA in  xilinx ISE their a single clock and depend on this clock I will synchroniz the adder and multiplier and other elements using  vhdl  code so depend on my code this clock will have maximum frequency value and during simulation their is an single clock I can see the change.

But when I work on LAB VIEW FPGA no single clock appear and many clock source appear

for example

in compilation result you can see two clock

 

And in xlinx log you can see two clock

And from this http://www.ni.com/white-paper/12942/en

you can see three source

please expain to us what is happen !!!!

best regads

[Esteban_B]

Hi mangood,

Could you post the VI? I would like to see how you are specifying the clock signal in the code.

Regards,

[mangood]

dear
i take the vi it from here

http://www.ni.com/white-paper/12942/en

please itract me