IP Integration node

[pegasuslogic]

Hi,

I loocked through many posts and searched in lots of materials, but could not fins answere to my problem.

I ma using LabVIEW 2011 IP integration node.

For sbRIO9642 I tried to integrate an IP synthesized for x3s2000 FPGA in Xilinx ISE as a ngc netlist file.

I always got error:

Annotating constraints to design from ucf file "toplevel_gen.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:59 - Constraint <TIMESPEC "TS_AsynchMite29"= FROM
   PADS(mIoHWord_n) TO PADS(aIoInt*) 0 ns;> [toplevel_gen.ucf(375)]: PADS
   "mIoHWord_n" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

It seams there is somethning wrong in intermediate constraint file.

Cam anybody help me to understandit is correct to integrate ngc netlist in LabVIEW FPGA.

Thanks,

Manuk.

[Tim_W. · Accepted solution]

Hi Manuk,

There appears to be more information on this particular error on the Xilinx website than in NI's resources. See this link for more details. To make sure that your VHDL is in the correct format for an IP node, follow the steps in this document.

Tim W.

Applications Engineering

National Instruments

http://www.ni.com/support 

[pegasuslogic]

Many thanks for your response.

Also many thanks to NI R&D, Chen Chen.

The problem comes from Xilinx synthesis options. By default, IO buffers are enabled in XST settings.

It is required to unselect this option. I have attached a snapshot of this option.

I compiled my IP core and integrated it into LabVEW FPGA. And it works!

Now I am evaluating CLIP technology. With these two techniques, FPGA development process becomes easier and faster.

I had many discussions at edaboard and opencores. Very few people know about NI technologies.

Again, many thanks for your response.

Manuk.