IRQ for average process of data with RT FIFO

[waiki.wu]

I am kinda stuck in this IRQ method. I am trying to read a batch of data and then process it to find the average. I got the averaging working (see the test.png) with the RT FIFO. However, when i used it in my project, the data read from the RT FIFO is the same for every line. I believe it is related to the IRQ wait, acknowledge and the one in the FPGA.vi. I am just wondering if someone could help me to understand where is the problem??

The mean.vi is just an sub vi i use to find the mean of each column.

Thanks

[Kareem_W.]

I've looked at your code and I'm a little confused. In your FPGA you write to both a FIFO and to "Data Read." In your host VI however, you read from "Data Read", write it to a new FIFO, and then read from that second FIFO. The FIFO that you initially fill (on the FPGA) is never used again. I am curious to know why you didn't simply read the data from your first FIFO (on the FPGA) into your host VI using an Invoke Method set to "read". This would eliminate the need to create additional FIFOs to move the "Data Read" values around the host VI.

[waiki.wu]

Yes, that was a mistake. I was learning the FIFO and the data reading from FPGA at that time. My understanding is that the FIFO can read data continuosuly, where the "Data read" only take one snaps everytime it runs. I am trying to read a batch of data to the RT FIFO and then take the average of it. However, i need to time the sequence so that it only read the data when the DO is turn on (this is used to trigger a relay for a power supply) I want to use the interrupt IRQ function but i don't know how to set it. I try to place the "wait for IRQ" at different place but still does not work. I hope you can help me out with that.

[Kareem_W.]

Can you please send a screen shot of your new host VI? (After removing the extra FIFOs and the Data Read code) This is important because I cannot guarantee that your code will work properly the way that it was coded before. Also, please try to include the whole block diagram. On the first screen shot that you provided of the host VI, part of it was cut off. Finally, what exactly happens as your code goes through the interrupts? How does it "not work"?