Import VHDL CLIP to Labview FPGA

[johnsnow34]

Hello everyone, 

I'm trying to import a .vhd file (VHDL code) to Labview FPGA as CLIP. But it seems to have a syntax error near code "package body". In this code, package body is empty, but that is not always necessary. Can it cause a problem in this code?

In addition, Labview says that it support only VHDL1993 or VHDL2002 syntax. Is that possible a VHDL version problem? I'm total new to VHDL and have attached the error information and the VHDL code. Anyone know where is the problem?

Any help will be appreciated.

Here is the error information:

Extracting top-level synthesis file information. Please wait...
Processing files...
Processing files...
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/NIFPGA/programs/Vivado2017_2/bin/unwrapped/win64.o/xelab.exe xil_defaultlib.conf058585D94A9B43218EA7A6E85ADDCEB1 -L xil_defaultlib -L unisim -L unimacro -L xilinxcorelib -L secureip -snapshot timetag_core_pkg -dll -prj clipsyn.prj
Multi-threading is on. Using 2 slave threads.
Determining compilation order of HDL files.
INFO: [VRFC 10-163] Analyzing VHDL file "C:/NIFPGA/iptemp/clipFC59D81E156944CAB7E0007607C44190/timetag_core_pkg.vhd" into library xil_defaultlib
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/NIFPGA/programs/Vivado2017_2/bin/unwrapped/win64.o/xelab.exe xil_defaultlib.conf058585D94A9B43218EA7A6E85ADDCEB1 -L xil_defaultlib -L unisim -L unimacro -L xilinxcorelib -L secureip -snapshot timetag_core_pkg -dll -prj clipsyn.prj
Multi-threading is on. Using 2 slave threads.
Determining compilation order of HDL files.
INFO: [VRFC 10-163] Analyzing VHDL file "C:/NIFPGA/iptemp/clipFC59D81E156944CAB7E0007607C44190/timetag_core_pkg.vhd" into library xil_defaultlib
ERROR: [VRFC 10-1412] syntax error near is [C:\NIFPGA\iptemp\clipFC59D81E156944CAB7E0007607C44190\timetag_core_pkg.vhd:96]
INFO: [VRFC 10-240] VHDL file C:/NIFPGA/iptemp/clipFC59D81E156944CAB7E0007607C44190/timetag_core_pkg.vhd ignored due to errors

Fix the above error and check syntax again.

--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Timetag core package
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: timetag_core_pkg.vhd (timetag_core_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 05-07-2013
--
-- version: 1.0
--
-- description: Package for timetag core
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: - 
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

package timetag_core_pkg is

  ------------------------------------------------------------------------------
  -- Constants declaration
  ------------------------------------------------------------------------------

  ------------------------------------------------------------------------------
  -- Types declaration
  ------------------------------------------------------------------------------
  type t_timetag is record
    meta : std_logic_vector(31 downto 0);
    seconds : std_logic_vector(31 downto 0);
    coarse : std_logic_vector(31 downto 0);
    fine : std_logic_vector(31 downto 0);
  end record t_timetag;

  ------------------------------------------------------------------------------
  -- Components declaration
  ------------------------------------------------------------------------------
  component timetag_core
  port (
    -- Clock, reset
    clk_i   : in std_logic;             -- Must be 125MHz
    rst_n_i : in std_logic;

    -- Input pulses to time-tag
    trigger_p_i   : in std_logic;
    acq_start_p_i : in std_logic;
    acq_stop_p_i  : in std_logic;
    acq_end_p_i   : in std_logic;

    -- Trigger time-tag output
    trig_tag_o : out t_timetag;

    -- Wishbone interface
    wb_adr_i : in  std_logic_vector(4 downto 0);
    wb_dat_i : in  std_logic_vector(31 downto 0);
    wb_dat_o : out std_logic_vector(31 downto 0);
    wb_cyc_i : in  std_logic;
    wb_sel_i : in  std_logic_vector(3 downto 0);
    wb_stb_i : in  std_logic;
    wb_we_i  : in  std_logic;
    wb_ack_o : out std_logic
    );
end component timetag_core;


end timetag_core_pkg;

package body timetag_core_pkg is



end timetag_core_pkg;

[MaxJoseph]

I have successfully imported VHDL into LabVIEW FPGA CLIP in the past. 

The error seems to relate to line 96. VHDL is very picky when it comes to syntax. 

Is this line correct syntax?

"package body timetag_core_pkg is"

[johnsnow34]

yeah, "package body timetag_core_pkg is" on syntax is right. Only the content of the package body is empty. I'v tried to delete the code "package body timetag_core_pkg is" and "end timetag_core_pkg;". But there is also error.