In a Labview Project, Vivado User defined CLIP Compilation Error

[levent34]

Hello, 

I designed a user defined, microblaze based CLIP in Vivado 2019.1 for Labview(2020 , 32Bit) Fpga of sbRio9603 board. I use this CLIP in my Labview Project. I get the compilation error message below during Labview Project compiling. I did not find reason of this error. Could someone help me please?

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [DRC INBB-3] Black Box Instances: Cell 'window/theCLIPs/d_uartgpio19_2_CLIP0/d_uartgpio19_2_i' of type 'd_uartgpio19_2' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port aSpiCs_n expects both input and output buffering but the buffers are incomplete.
INFO: [Project 1-461] DRC finished with 1 Errors, 1 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.872 . Memory (MB): peak = 1485.574 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
6 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.
opt_design failed
::ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.

while executing
"opt_design -directive "Explore""
(file "C:/NIFPGA/jobs/ay5ZZho_ggbZSKq/optimize_logic.tcl" line 4)
invoked from within
"source "C:/NIFPGA/jobs/ay5ZZho_ggbZSKq/optimize_logic.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Wed Feb 2 18:00:28 2022...

[John80 · Accepted solution]

You may have forgotten to wire up a pin, or you may have forgotten to copy the implementation file (.dcp/.v/.vhd) to the same directory as your top-level VHDL wrapper for your CLIP?

See:

https://fpganow.com/index.php/2021/02/19/dealing-with-the-vivado-drc-inbb-3-black-box-instances-issu...

[levent34]

Hi John,

Thank you very much for your answer. The compilation error was resolved with the document you sent me. My labview project is compiling now but my user defined CLIP doesn't work correctly. I have added a constraint(xdc file), it works in vivado but not in labview project. I get an some warnings in  Labview compilation status window(In Xilinx log part). I highlighted the warnings related to my CLIP design. My ports seem unconnected in labview, I checked that they are connected in vivado implemented fpga device. 

xdc is;

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
#set_property IOSTANDARD LVCMOS33 [get_ports {clk_100MHz}]
#set_property PACKAGE_PIN E3 [get_ports {clk_100MHz}]

#set_property -dict { PACKAGE_PIN "D7" IOSTANDARD LVCMOS33 } [get_ports {uart_rtl_0_txd}]
#set_property -dict { PACKAGE_PIN "E7" IOSTANDARD LVCMOS33 } [get_ports {uart_rtl_0_rxd}]
#set_property -dict { PACKAGE_PIN "E5" IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports {reset_rtl_0}]
set_property -dict { PACKAGE_PIN "D5" IOSTANDARD LVCMOS33 } [get_ports {Op1_0[0]}]
set_property -dict { PACKAGE_PIN "D3" IOSTANDARD LVCMOS33 } [get_ports {Res_0[0]}]

Regards