Is there a way to slow FPGA 7813R board below 40MHz ?

[Diego2000]

Hello:

>  After compiling for 4 hours, I get a Timming Violation error.

    Requested Rate: 40 MHz     (I did not request)

    Achieved Rate: 31 MHz        (Lower than 31 MHz would be ok)

>  I am using an FPGA 7813R PCI card in a Windows XP enviroment.

    The FPGA board runs at 40MHz, 80MHz and Higher...

> Is there a way to slow down the main clock to say 10MHz or even lower to 4MHz. ?

    I tried to use derived clocks but apparently the 7813R board
    does not support lower clocks? Can I physically change the board clock?

    Is there a workaround? I'm also using 80 I/O pins and 40k Bytes

> The number of Slices is about 99%

>  Maybe I need to use a different board?

thank you for the help...

\\carlos

[Robbob]

RTD,

Two part answer for you.

First, the simple one: Yes, you can make derived clocks lower than 40Mhz that can be used for Single Cycle Timed Loops.  Right click on the 40Mhz onboard clock in your project, ->New FPGA Derived Clock. This is not the Master timebase, but rather the timebase used for single cycle timed loops.

The better answer is: If you are using 99% of your slices, you are doing way too much and not optimizing your code. If you are using DMA FIFOs, make sure none of them are larger than 8152 elements. If you are using fixed point, reduce the number of bits allocated to word length(do you really need 24 bits to store a number?), learn how to PIPELINE! - instead of doing 10 operations in series each time the while loop executes, use shift register to do 10 operations in parallel.  The reason it is taking 4 hours to compile is that you have so much you are trying to fit into X number of gates, and the reason you are getting a timing violation is because you are trying to do too much in one loop without pipelining.  The 7813R is a 3 Million Gate FPGA, which is plenty of room to run most applications, go back and take a look and see where you can optimize.

[Diego2000]

Hello Rob:

0.  By the way, I am using a regular WHILE loop.

1.  I did try to use a Derived clock from 40 MHz but the board does not support it ? (PCI-7813R)

     If it does not support it which board would you recommend?

2.  I am using RAM Memory (40%) and not DMA FIFOS. The reason is that I need to have

     8 independant Circuits on the FPGA and each circuit would need 1 FIFO. Means that I would need

     8 FIFOS. I believe the board only supports 3 FIFOS ? Please correct me if needed...

3.  Please note that 2 circuits fits nicely, but when I add 2 more circuits to a total of 4

     Then my Timming problem starts. Eventually I need to run 8 circuits which probably

     means that I need to buy 1 more board.

4.  I would be glad to run at lower rates such as 10 MHz, 4MHz. I do not need to run

     at 40 MHz. There must be a way to physically change the main clock on the board.

thanks for your help...

\\carlos

[Robbob]

Sorry if you misunderstood the post, but derived clocks are completely allowable on the 7813.

The Main Clock can be upped to 200Mhz, but for lower frequencies, use a derived clock and a timed loop, as shown.  A timed loop can use a derived clock as its clock source.

I am still worried that you are using 99% of your slices, this tells me that too much is going on in your code anyways. And how are you passing your data from the FPGA to the host if you are not using DMA? I am assuming you are using the RAM to pass data between loop, but how are you getting this data to the Host?

 

Message Edited by Rob_K on 10-27-2008 03:40 PM

[Diego2000]

Hello Rob:

Sorry for the delay. I was gone for a week...

1.  Ok, Derived clocks are allowable on the 7813R.

2.  Question: Can I use derived clocks with regular timed loops?

     OR does it have to be a Single Cycled Timed Loop?

3.  Inside my loop, I have several FOR loops to emulate Read/Write SPI

     Bus comunications.

     Is it true that I can NOT use FOR loops in a Single Cycled Timed Loop?

4.  I am passing data from the Target to the Host by Transfering Memory reads into

     indicators and Flags to handshake when data is available and when data is taken...

thank you,

\\carlos

[Robbob]

Carlos,

The derived clocks are meant for single cycle time loops (SCTL), but we can make them function just like any other while or for loop. The big reason to use SCTL is to ensure that the code inside the loop is completed in x micro or milliseconds every iteration, every time.

It is true that you cannot use for loops inside a SCTL, but you can easily make a SCTL into a for loop by using shift registers and a custom counter.

Every Indicator on the front panel is taking up FPGA resources, you could still use flags and pass all the data through a FIFO.  80 I/O pins, so I am assuming at most 80 boolean values, maybe a few other values you computed.  You could flag your host that the data is read and then read x number of elements from the FIFO.