LABVIEW cRIO9074 Current voltage measurement

[meharda_92]

But I think that the issue it not only for scanning internal, I am fine with 10ms scan interval but even at this time interval the measurement was not proper. may be there is any other issue while method of reading these parameters (V/I).

Because once before I measured it correctly waveforms but when tested after few months latter with same program/same method, I did not getting the results.

Thanks for prompt replies.

[meharda_92]

I am facing same issues in power measurement, my query link is below

Re: LABVIEW cRIO9074 Current voltage measurement - NI Community

[cy...]

based on the screenshots, multiple "same" AIO variables are redundant, but I assume you will use different channels in the actual case, since you labeled it differently

some points of "probable" improvement:

- use circular buffer, ever growing arrays are never a good case, especially in old cRIOs with less memory

- configure variable to output its timestamp as well, that way you can probably have a better representation of your waveform

- if you want to venture into FPGA but maintain RT, it is possible with FPGA interface

- is that VI on your RT level, if I am not mistaken 9074 is still pharlaps, no? no embedded UI, why plot charts? and why not timed loop, there is no proper timing in the screenshot

- if you have invested in the power toolkit, wouldn't it make sense to get better waveforms?

just dropping in because of past topic followed... currently following other SaaS closely 😅

[meharda_92]

I have used different AIO for phase wise measurement of V/I and I want to solve it using RT mode only and NI current/voltage modules connected in cRIO9074 for measurements. 

I plots charts of V/I waveforms but they are not accurate. 

Can you help me out to how to get better waveforms and power-RMS values measurements. sample code files are also attached previously. 

Thanks

[cy...]

read earlier comments

[meharda_92]

considered but did not find any solution, only suggesting to go with FPGA mode

[rolfk]

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@meharda_92 wrote:

considered but did not find any solution, only suggesting to go with FPGA mode

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Exactly! You can keep insisting that the mountain needs to come to you, but usually that is wishful thinking, at least in our universe. Maybe there are others where this would be possible. 😀

I also mentioned that you should have bought a cDAQ chassis instead if you do not want to do FPGA programming.

[cy...]

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@cy... wrote:

based on the screenshots, multiple "same" AIO variables are redundant, but I assume you will use different channels in the actual case, since you labeled it differently

some points of "probable" improvement:

- use circular buffer, ever growing arrays are never a good case, especially in old cRIOs with less memory

- configure variable to output its timestamp as well, that way you can probably have a better representation of your waveform

- if you want to venture into FPGA but maintain RT, it is possible with FPGA interface

- is that VI on your RT level, if I am not mistaken 9074 is still pharlaps, no? no embedded UI, why plot charts? and why not timed loop, there is no proper timing in the screenshot

- if you have invested in the power toolkit, wouldn't it make sense to get better waveforms?

just dropping in because of past topic followed... currently following other SaaS closely 😅

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@meharda_92 if this does not work, then FPGA it is