LV FPGA project sizes

[Intaris]

When I try to organise my VIs for an FPGA project in my project I notice a huge increase in the size of my lvproj file.  It seems that LV sotres an appropriate signature value for each and every VI in my project as if it was a top-level VI.  While I understand the need for this in essence, given the absence of a build spec for 99% of these VIs, isn't this a bit of overkill?

We use a custom CLIP and adding the information required for this CLIP to the signature for each and every file is exploding our lvproj size.

I am aware that the workaround is to only include the top-level VIs in the project but I'd really rather be left the choice without having my SVN commits being negatively affected.

[David-A]

You can avoid this behavior if you organize your VIs inside an lvlib and add the lvlib to the fpga target.

[Intaris]

OK, that might work.  But can't a single VI within an lvlin also be a top-level VI? Sounds like not completely logical behaviour.  Having the VI a member of a class doesn't have that effect.