LV FPGA signal IO timing

[Rafal_Kor]

What would be the most code efficient way to measure how many 1usec ticks lapses between rising edges of 2 different DI's in Labview FPGA such as sbRIO-9629?

[ZYOng · Accepted solution]

Add a U32 feedback node or shift register in a timed loop. On the first rising edge, reset and add one on each tick. On the second rising edge, stop and return the counter value.