LabVIEW FPGA: The compilation failed due to a Xilinx error (Synthesized error)

[ashrafayasrah]

Hi all,
I have converted a Matlab Code to VHDL code via Matlab tools. The VHDL code is imported into Labview FPGA through IP integration node (please see the attached), it imported successfully.

* I am using MyRio 1900, Labview FPGA (a version of 2018).
*There is only one "IP integration node" in the "timed loop" "5MHz''.
*It is working correctly when I am using "FPGA target" -execution mode- as "Simulation".
However, I got "LabVIEW FPGA: The compilation failed due to a Xilinx error." (Synthesized error) when I am using "FPGA target" -execution mode- as "FPGA target". Please see the attached.

Please note that I have imported a small VHDL code (part of the main code) into Labview FPGA and it was compiled successfully.

I would be greatly grateful if someone could give some suggestions. Thanks in advance.

[Terry_ALE]

What do the other drop downs say in terms utilization. You show configuration and xilinx log. 

[ashrafayasrah]

Thank you for your response
Please see the attached (Configuration & Xilinx log)

[Terry_ALE]

See https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgadialog/fpga_compile_help/ under Reports.

How far along does the compile get?  If any of these reports are available, then post screenshots.  They will tell us high level info before digging into the Xilinx logs.

[ashrafayasrah]

Actually the problem was due to some of the "for loops" have a variable limit, so the problem is gone after I changed it to a fixed number. BUT the compiling prosses started to take more than 2 hrs without finishing the compile. So, after dividing my code to half (50% of the code) and import it again into Labview FPGA, I got a new problem "LUTs resources". Is there any suggestion to reduce the LUT usage.

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [Place 30-640] Place Check : This design requires more Slice LUTs cells than are available in the target device. This design requires 30569 of such cell types but only 17600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.
ERROR: [Place 30-640] Place Check : This design requires more LUT as Logic cells than are available in the target device. This design requires 29401 of such cell types but only 17600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.
ERROR: [Place 30-640] Place Check : This design requires more LUT1 and LUT2 and LUT3 and LUT4 and LUT5 and LUT6 and RAMD32 and RAMS32 and SRL16E and SRLC32E cells than are available in the target device. This design requires 36688 of such cell types but only 35200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ToplevelClkVirt' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [C:/NIFPGA/jobs/X8kue09_Lbc7Dxn/toplevel_gen.xdc:377]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1571b0fb1

Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1505.305 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 1571b0fb1

Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1505.305 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 1571b0fb1

Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1505.305 ; gain = 0.000
14 Infos, 42 Warnings, 0 Critical Warnings and 5 Errors encountered.
place_design failed
report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.561 . Memory (MB): peak = 1505.305 ; gain = 0.000
::ERROR: [Common 17-69] Command failed: Placer could not place all instances

while executing
"place_design -directive "Default""
invoked from within
"if { [catch {place_design -directive "Default"} error_message options] } {
report_utilization -file "toplevel_gen_map.xrpt" -format xml
return..."
(file "C:/NIFPGA/jobs/X8kue09_Lbc7Dxn/place.tcl" line 6)
invoked from within
"source "C:/NIFPGA/jobs/X8kue09_Lbc7Dxn/place.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Sep 10 17:11:21 2020...

Compilation Time
---------------------------
Date submitted: 9/10/2020 5:02 PM
Date results were retrieved: 9/10/2020 5:11 PM
Time waiting in queue: 00:10
Time compiling: 08:52
- Generate Xilinx IP: 00:00
- Synthesize - Vivado: 07:32
- Optimize Logic: 00:43
- Place: 00:25