Hi I am writing LabVIEW FPGA programs to my FlexRIO PXIe-5774 with LabVIEW 2019 sp1 64-bit. I am using multiple FFT Express VIs which seem to be very tight on time and resources. Thus my compiles take 6-7 hours. My problem is the compilation process. The variations of my code seem to just sometimes cause ridiculous timing violations when compiled. This happened today: It's hard to fit anything into 0 ns and even harder when you aren't even told what it is that you should be fitting to that time. Another case: I made a version 0.8 of my code and when it was compiling I built on top of that code and made version 0.9 and 0.9.1 where I only added more code to the existing code. The 0.8 version failed because of Timing violation that was equally as unhelpful as the one I showed you but the version 0.9 and 0.9.1 compiled fine and worked like they should. I understand that the compile process is a bit random but this is ridiculous and wasting my time. Is there any way I could try to avoid needing to make small changes to a 'Timing violation' code and recompiling again hoping that it won't fail again? Any tips on better FPGA development? I am mostly compiling on the LabVIEW cloud compile service. Thanks for any input: Aarni

LabVIEW

LabVIEW FPGA Timing violation confusion

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I tried that but I still got a timing violation. I compiled two copies of the same exact code, one with 'Optimize congestion' and on with 'default'. The default compiled...

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LabVIEW FPGA Timing violation confusion

Re: LabVIEW FPGA Timing violation confusion