LabView FPGA Sequence Structure Timing

[kopiad]

I'm currently investigating if a NI 7813R Reconfigurable I/O Board has enough performance for our application.

In the SPI Example "FPGA SPI Communication.vi" at <http://zone.ni.com/devzone/cda/epd/p/id/3458> there is a flat sequence structure in the lower while loop.
Will the data be read (in the second sub diagram) directly after the rising clock edge (in the first sub diagram) or will it be read at the next "FPGA master clock" (40MHz)?

Regards
Hans Forssell

[BruceAmmons]

I couldn't track down which sequence you are talking about, but I may have an answer:

On FPGA, everything in a timed loop executes once per clock pulse (40 MHz).  If your sequence is inside a timed loop, everything will execute at 40 MHz.

If it is a regular while loop, it will not execute that fast.  Code is relatively slow outside a timed loop.  If I understand correctly, each operation or two takes a clock cycle.  Your entire while loop rate could be many clock cycles depending on the complexity of the code.

Bruce