Labview FPGA USRP x410

[BEZENCHUK]

FPGA vi does not compile with errors.
Also in simulation mode, an error occurs in the block opening of the transmitter usrp with a user bitfile -1633 in the host vi.

[Terry_ALE]

Are you trying to run simulation mode with the bitfile?  Simulation mode should be pointing to the FPGA VI.

How much RAM do you have on the computer that you are compiling on?  I think the RFSoC needs something like 32-64 GB of computer memory (Vivado requirement) to compile.

[BEZENCHUK]

Thank you for your reply. In the block "open fpga vi reference" specifies correct vi fpga. Previously the block "open TX session with a custom bitfile" did not lead to an error, I had a successful simulation. I did not have any significant changes in the program. At one point both compilation and simulation stopped working.

I completely reinstalled labview and created a new project several times.

Also, when I turn on the simulation of vi fpga directly (running fpga vi), an error appears in the "unknown location" -2147467259.
My computer has 32 GB of RAM. 
Again, previously the compilation was successful. Compilation errors indicate placement errors, but I do not have the qualifications to identify them. 

My project has embedded IP cores through integration and .dcp files, is this not a problem for the compiler?