Labview FPGA: Using the DDR Clip outside SCTL?

[Ciaran27]

Hi Guys, i have written a bit of labview code to use the DDR clip however im using it inside normal while loops. 

I believe this is causing strange behaviour on my output as i can generate a clock at 40mhz using the DDR clip (inverting the falling edge), though my usual pulse generating code isnt working properly and only keeps the line high for one cycle before falling low again. 

I believe this is due to my implementation of the ddr clip outside of a single cycle timed loop but was wondering if anyone had an experience with this. 

Any help is greatly appreciated 

Regards 

[Terry_ALE]

Which NI FPGA card are you using?  Which version of LabVIEW?

[Ciaran27]

I am using the 7961-R with the 6583 MLVDS IO card. All on LV 2018

[Terry_ALE]

I would keep the DDR in the SCTL.  The existing LabVIEW FPGA code could FIFO the data over to the SCTL.  Have you tried that approach?

Ultimately you may have to move your code to run in an SCTL as it will need to keep up with the rate of the CLIP's expected rate.

[Ciaran27]

I am using an NI example of i2c which uses normal while loops. 

do you think i could use a fifo to feed the IO data from the normal while loop to the SCTL?

I should also mention the IO is accessed in numerous places in the code simultaneously which i believe could complicate matters