Labview FPGA--hardware clocking error

[u436]

Hello.

I was having problems executing a labview programme on the FPGA. The programme compiles without any errors. But when I execute it, it gives me an error about the clocks. The error messages are attached.

I am not using any external clocks.

We managed to solve the problem by adding more pipelines in the FPGA vi. The vi is now running, but it stops responding after a while giving the same error message.

The FPGA target is RIO0, PXIe-7965R with a NI5762(-02) adapter module.
The Chassis we are using is a NI PXIe-8133.

Do you know how I can solve this problem?

Cheers,
Syed

[Ben-N]

Hi u436,

Do you have any derived clocks on the FPGA that you are using for any timing in your program?  Also, are you using the PXI backplane clock as the timing for anything?  The error you are getting is from the FPGA, so if you are also referencing the timebase on the PXI chassis, this error might be occurring.

Let me know what the situation is and we can work through this.

[u436]

Hi Ben,

Thanks for your reply.

Yes the FPGA has a 40 MHz onboard clock and I am using a 60MHz clock derived from the 40MHz clock to clock a single-cycle-timed-loop.

I am also using the IO-Module Clock 0 at 125MHz for the data acquisition.

These are the two clocks used on the FPGA.

I also have a 100MHz sine wave out from a PXI 5404 frequency generator that is used in the real time target...but I don't think this is related to the problem.

Cheers.

[u436]

Hi Ben,

Attached is the XilinxLog file if that helps.

Cheers.

[Ben-N]

Hi u436,

You mention that you are using a 125MHz clock for data acquisition from from the IO Module.  Are you using the default clock rate for the socketed CLIP?  Did you do any configuration on the IO Module's clock?  You also mentioned in your first post that by adding more pipelines to the program, the program started running, but now it gives the error after running for a little while. Is it possible that you are trying to get your SCT loop to run faster than the amount of time you are alotting for that process to finish?  I'm wondering if your loop isn't able to run quickly enough and that your two clocks are slowly shifting, eventually giving you this error, which was slowed down by pipelining the VI.  Have you benchmarked the process that is running in the SCT loop?

[u436]

Hi Ben.

Thanks for the reply. We have a NI 5762(-02) IO Module and the default clock rate is 125 MHz. It is set to compile for that single frequency. I did not configure the clock, just used the default setting.

It is possible that we were trying to run the SCT loop faster than the amount of time needed for the process to finish. I did not benchmark the process running in the SCT loop. Since it compiles without any timing error, I would think that the processes could run in the single clock tick.

Just to clarify, there are two SCT loops. The 1st loop at 125 MHz writes some data into a VI-scoped FIFO. The 2nd loop at 60 MHz reads data from the FIFO and does some processing to the data.

Cheers.

[Sev_K]

Hi Syed,

We need to figure out if the errors that you are getting are related to the 5762 module or other hardware/clocks in your PXIe chassis. Could you remove the loop that aquires data from the 5762 module and recompile your code to check if you will still get the same errors. Let me know the results