Labview FPGA, resetting input module using FPGA I/O node outside flat sequence

[Austin-Downey]

Greetings, 

I have a very simple data logging application (MWE) that collects a voltage signal using a NI 9229 mounted in a cRIO-9054 and returns it to a chart. The only way I am able to get it to work is to first stop the modules, then restart the module using a flat sequence as shown below, 

If I don't reset the module, it simply returns all zeors. However, I really do not think I should be using a flat sequence to reset the module. I tried linking the I/O nodes together using the "FPGA I/O In" and "FPGA I/O Out" wires, but that does not work as they change format. I am trying to figure out the "correct" way to enforce a data-flow on these modules. How should I do this? 

A few other notes:

1) I know I can enable the error terminals, but this uses more FPGA resources, and would like to avoid this if I can. 

2) This issue came up when I was looking at a much more complicated code, so while this application works just fine, I would like to fine the optimal way to do it so my later code is more complicated. 

3) Is there a  way to "reset" the module for the host VI? I have the "Reset (Invoke Method)" set up in my host VI, but this does not seem to do the trick. I have also attached the host VI below for clarity. 

The code is attached if that helps. I wrote it in LabVIEW 2020 but saved in LabVIEW 2016. 

[Austin-Downey]

NI support helped me out. 

The issue is that I have a NI-9229. For this particular module, it is required to be started to begin the acquisition. This can be seen here,

https://zone.ni.com/reference/en-XX/help/370984T-01/criodevicehelp/crio-9229/

I need to explicitly indicate it in my code (as I am doing it with the Mod1/Start method) to start it. I should stop it at the end of my code, the start. Therefore, this module requires a flat sequence structures or error cables.

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