07-08-2018 10:52 AM
Hi guys,
nowadays im trying to develop a generic TARGET vi to read binary files to the DRAM of the FlexRio.
i need to load 3 diffrenet binary while each file starts from different address at the DRAM , and also use only one DMA.
I have an initial ADR that read from the HOST , and im using a shift register as counter . The problem is with the next address , casuse i cant initialize the shift register with the new address.
07-08-2018 12:19 PM
Could you break up the problem into a simple state machine? If you always send the starting address, file size, and then the data you could wait for at least two elements in the queue and once you have that information you set the starting and ending address. Count from the starting address until you reach the ending address and then go back to waiting.
07-10-2018 02:30 AM
I build a state machine , but one of my Address counters only increments once ("TMP_Final ADR).
i cant figure why . i think maybe its because of a bad handshake between the DMA and the DRAM.