--- As far as implementing a solution for the output glitches:
1. The simplest approach would be an R-C filter (output goes through a Resistor to a Capacitor, then to 0VDC; use the signal between R & C). You can use two stages for even better clean-up.
2. You could also use a little circuitry to shift the voltage from 1..9V to -4..4V, and avoid the glitch. But it looked like there's another (smaller) glitch at a higher value, likely +/- 2048 in the raw value. So you may need to avoid that, too.
3. You could use two outputs, and use a resistor divider between them (that can be combined into an R-C filter, too). One output could be 0.1..10V, and the other -10..0.1V. The average would be -4.95..+4.95V. The software would need to output positive values on one channel, while keeping the other at -0.1V, and vice-versa for negative values.
If you have an R-C filter, and need high frequency outputs (R-C filters attenuate/reduce high frequency signals), you can pre-filter the output to amplify the higher frequency. It's been 20 years since I've made a compensating filter, and don't remember most of the details--it resembles a high-pass filter, but adds the unfiltered signal, too (i.e. out[n] = y[n] + a*(y[n]-y[n-b]), where 'a' and 'b' are found experimentally).
--- As far as the noisy input:
I'm shocked that it would be that noisy. A little noise isn't much of a problem for most PID applications (unless you are driving a valve). But that much is ridiculous. Especially with filtering (7X box filter). (by the way, the FPGA usage will be a little lower if you use 8 instead--1/8 is a simpler binary value).
Could you add the original (unfiltered) input to the chart? I don't think there is anything wrong with the math, but there is a small chance. There may be a clue how to fix it, too. Sometimes an occasional bad value can be filtered better using the Median instead of Mean/Average, or by removing the min & max, then averaging the rest.
With the triangle wave, it looked like adding a 1uSec delay fixed it... That isn't a great surprise, since a lot of A/D Converters behave poorly when they are polled too quickly. 3uSec ought to have done as well or better. It makes me suspicious that 3uSec has a similar problem. Please try a few different delay periods, and see if anything cleans up the signal. I couldn't find any clues in the documentation, but didn't look very hard, either.
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CLD, CPI; User since rev 8.6.
