Labview myRIO FPGA programme. Write to an excel spreadsheet

[azwa122222]

Hi, 

Attached is my current VI. I just want to acquire data that can be input to excel. Currently, it produces a very disjointed set of data. I just want my time in 1 column (either elapsed time or time stamp - I dont mind), and the next four columns to represent my 4 displacement values. I just want a quick snapshot and the ability to record 1000 samples when i press the button. Each sample should be read in 1 second. 

[ZYOng]

1. I recommend using interleaved data transfer. See Transfer multiple channels of data through one DMA FIFO on FPGA
2. The number of sample should be controlled by the FPGA, not the 1000ms wait on the host.
3. There should be a Wait(ms) node in the outer while loop for the host. The while loop will run at maximum speed and starve your CPU when the Read button is off.

[Bob_Schor]

Am I correct that your program uses the myRIO as the "Target" for a LabVIEW Real-Time Project, with Host code running on the "My Computer" part of the Project?  In such a model, the code running on the myRIO Target acquires data and streams it to the PC Host where it can be "streamed" to disk.

Under this model, the Host PC has Giga-bytes of memory, Tera-bytes of disk storage, and can run software (LabVIEW Real-Time) that can communicate with the myRIO.  The myRIO, by contrast, has orders of magnitude less memory and orders of magnitude less storage.  

In this three-level software structure, the PC runs the User Interface (including graphic displays) and manages storage (both in memory and on disk) and delegates to the myRIO the "Real-Time" aspects of the code.  I've generally linked Host and Target through Network Streams (though others hae used other TCP/IP-based transfer mechanisms) with at least three streams -- Host-to-Target messages, Target-to-Host messages, and Target-to-Host data streams bound for planned disk destinations.

Finally, there's the FPGA running on the myRIO Target.  This is where you build your custom "hardware/protocol" code.  In my case, I programmed the FPGA to talks SPI to 16 A/D chips-on-boards allowing me to simultaneously sample 16 channels at 10 kHz to monitor 16 Pulse Generators (also controlled by the FPGA).

Not sure how your code fits into this model.  Are you ready to run on three different processors, communicating (bilaterally) with their "neighbor" processor(s), each doing their "designated" part to accomplish your goals?

Bob Schor

Bob Schor