Latency Time of Data Transfer between the FPGA and RT Host

[pegahm]

I am interested to know the latency time for transferring data between the FPGA and RT Host for both data transfer methods (Programmatic Front Panel Communication and Direct Memory Access). I have looked at the NI document on this topic; however, I could not find the actual numbers on the latency time. I am interested to get the numbers for both methods of data transfer.

[crossrulz]

How fast do you actually need?

If you are worried about this, then I would be trying to get more into the FPGA.

[pegahm]

If I could get a sub ms on the turn around (loop back) from the time the signal goes high till I see it back on the FPGA.

[crossrulz]

What all do you need to do with the signal?

For a simple loopback, you will have no problems with the 10s to 100s us loop rate on your RT.

[pegahm]

That's great, thank you! I am not doing heavy operations on RT, it could be as simple as just inverting a signal and send it back.

Does both data transfer methods I mentioned earlier have somewhat similar latency times?

[crossrulz]

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@pegahm wrote:

That's great, thank you! I am not doing heavy operations on RT, it could be as simple as just inverting a signal and send it back.

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In that case, just keep it all in the FPGA.  It will make things simpler.

But for higher speed, I typically use the DMA FIFO to pass data to/from the FPGA.  The front panel controls I typically leave for the intermittent tags.

[James_McN]

Hi Pegahm,

Crossrulz is right, if you can do it all on the FPGA then that is a good choice but to answer about the latency numbers - as ever it depends!

The front panel communication requires the CPU to be involved so this will determine latency. From memory I have measured this before to be around 10us but I forget which target - almost certainly a  cRIO.

The DMA FIFOs will normally have a higher latency by virtue of the back that it is a FIFO buffer and is transferred from FPGA to host based on a set of triggers. These are:

1. FPGA side buffer is quarter full.
2. FPGA side buffer has at least 512 bytes (A PCIe packet)
3. An eviction timer will make sure it is transferred (specified by NI as around 1us)

Of course this is just the engine. This doesn't account for time fetching the data in RT.

So those are the factors that contribute and it looks like they are probably similar - at the end of the day I would pick the method that fits the data. Are you transferring a waveform? Then DMA FIFO. Do you just want a current value? Use the front panel.

 There's a lot more to go wrong with a DMA FIFO that could affect the latency (if you don't keep up with reads the latency will shoot right up) so I would avoid them if latency is important for that reason.