List of running FPGA simulators?

[lsstpkubanek]

Is there a way to show running simulators? I have a bit complex FPGA code, and it sometimes keeps running in simulation when I expected it to stop. FPGA modules are then distinguished by doted "Run" arrow, I can't edit those modules, and when I tried to run another FPGA in simulation, it either crashed or shows "Connot run simulation, as another simulation is running". Knowing which simulation, if that was started through Desktop Execution Node (which I use extensively to run tests) or otherwise, along with a button to kill FPGA simulation would help. LabVIEW 2018, but I can update to 2020 if that will fix the problem.

[Intaris]

Simulation on FPGA for anything apart from trivial code is a one-shot experience for me.

I run a simulation, stop it and before I try to do anything else, I restart LabVIEW. Probably a bit dramatic, but coming from LV 2015 where things were definitely worse than in 2019 (Can't comment on 2018 vs 2019, sorry) it has become a habit.

I DO know that the experience between LV 2015 and 2019 has improved significantly. Given the complexity of what's being done behind the scenes, I'm happy it even works well at that level.

[Terry_ALE]

Have you set any of the SCTL (disable enable chain) settings to anything but the default?

Are you calling a close FPGA VI reference from the host?

Can you post your host code?

[Intaris]

I am not able to disable enable chain because our clocks are not free-running.

No, when I simulate, I simulate purely in "interactive" mode on the FPGA. I never involve anything outside of the FPGA target. I have a whole load of test VIs specifically for executing in simulation mode on the FPGA in interactive mode.

[Terry_ALE]

Understood.

How do you test DMA-FIFOs in interactive mode?

Do you use conditional disable blocks for running in simulation mode?

[Intaris]

Ah, now we're getting into the details. I absolutely hate conditional disables on FPGA when trying to use interactive mode. It's hell.

I test DMA FIFOs by feeding them in standard FIFOs and reading them on the top-level test VI.

You know that if you configure a FIFO reference on a connector pane as FIFO, with only a read or write interface, then you can actually connect a DMA reference to it and it works fine. This allows to switch to "standard" FIFOs for testing. I do this all the time. I NEVER place a DMA Read or Write Node linked to a project item. I always feed in the references from the top-level VI. That way I keep the flexibility for testing.

I do the same with as many "project" items as I can.

[lsstpkubanek]

I have the code on https://github.com/lsst-ts/Modbus_Processing_Unit. There are a few unit tests done using the Desktop Execution Node (DEN), and after a lot of pain, it works as expected. A major discovery was realizing for DEN, you have to set clocks to something else then default 1 tick, if you want to execute anything reasonable - otherwise LabVIEW obviously don't finish the first run, but surprisingly crashed on second run (again, LabVIEW 2018).