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Master/slave design with multiple slaves in SubVIs

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Hi,

 

I've always used the classic master/slave design. But now I need a master/slave design in which one main master loop has 3 slaves and each slave, in its turn, has 4 slaves.

 

I've finished my application with the main master, one slave level 1 one the slave level 2 ('subslave'). As I don't want to copy/paste the code of each loop, I was thinking about creating a subVI for each loop and just link them in a main VI.

 

To make it clear:

 

Main VI

-Master (subVI x)

 

--|

-->Slave 1 (subVI y )

----|

---->Subslave 1 (subVI z)

----|

---->Subslave 2 (subVI z)

----|

---->Subslave 3 (subVI z)

----|

---->Subslave 4  (subVI z)

--|

-->Slave 2 (subVI y )

 

----|

---->Subslave 1 (subVI z)

----|

---->Subslave 2 (subVI z)

----|

---->Subslave 3 (subVI z)

----|

---->Subslave 4  (subVI z)

 

--|

-->Slave 3 (subVI y )

----|

 

---->Subslave 1 (subVI z)

----|

---->Subslave 2 (subVI z)

----|

---->Subslave 3 (subVI z)

----|

---->Subslave 4  (subVI z)

 

 

 

 

But how can I do it? How will the notifier send the notification to the slave if the master is running in another subVI?

 

Regards,

Gracietti 

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Solution
Accepted by mgracietti

You pass the reference that was obtained for the notifier to the SubVI through the front panel connector.  In the subVI, you will create a control on the front panel that is the same datatype as the reference that is created in the main VI.  Attach that control to the connector panel of the subVI.  Now when you obtain the reference in the main VI, you'll pass that wire to the subVI.

 

It is also possible to use named notifiers.  When you obtain the notifier in the main VI, give it a name.  Obtain a notifier in the subVI and give it the same name.  Now you've created two different reference wires, but the point to the same notifier because of the name you gave them.

Message Edited by Ravens Fan on 02-14-2010 11:24 PM
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Thanks Ravens!

 

The problem was solved with the named notifiers. Quite easy and simple solution.

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Hi,

   one question r u using any hardware  because i also need to design a master slave logic .Master is my chip and the slave will be VI,and also it supports serial comunication

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adding to the above i also don't know how to select the slave(which is VI) i have 4 pins which will be connected to the slave so atmost 4 slaves can be connected.

Do i need to use any NI hardware for communication/Selecting the Slave?

I will be very grateful if any one can give me solution

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Hi karthikk,

 

either you enter old threads with your question or you create your own thread. But don't create double posts!

 

Please stick with your own thread!!!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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