Methods to reduce cluttering in a FPGA diagram?

[Pierre_F]

After several months of programming, my FPGA code has become very big. You can see below the navigation windows, and how is my screen size compared to the code

I had to devellop 10 parallel process timed with different rates, and using approximately 50 I/O registers, 30 input/output to Crio9047, 3 internal FIFO, 3 DMA FIFO,  2 IRQ, 4 internal registers.

Do you know if there is tips to reduce the code cluttering?

What about subVI for each process? is it compatible with all this stuff?

regards

[Bob_Schor]

If you post the actual FPGA VI, we could look at it closely, perhaps suggest how to get rid of extra "white space", and "pack" the code more efficiently.  There also might be other ways to achieve some of your objectives by using other code, but looking at a low-contrast tiny "picture" of an 8-screen piece of FPGA code would certainly help us to make possibly-useful suggestions.

Bob Schor

[santo_13]

You can always modularize each functional block into SubVIs and call them in the Main VI.

[Intaris]

Yes, Sub-VIs is the way to go initially.

I've yet to find anything on FPGA targets that cannot be incorporated into a sub-VI. I have actually found that some modifications I've made in order to better support making all of my FPGA code into sub-VIs (or modules if you will) has led to better code.

I have now ordered my code so that ALL resources allocated in my FPGA code are instantiated on the top-level diagram (where possible - DMA Channels still must be project-defined) and passed into the sub-VIs as parameters. This allows me to re-use the sub-VIs with different inputs for testing.

Did you know that a DMA Channel (Target to Host) and a Target-scoped FIFO with only the Write port selected can be interchanged when fed into a sub-VI? I use things like this to create on-FPGA debug VIs where I can isolate individual portions of my code for interactive testing. It has helped a lot in tracking down issues.

If you create a FIFO reference as a FP control....

You can configure it.....

As either a "Write" or "Read". If your sub-VI only requires one interface, make sure to only select what is needed. With this approach, you can then, for testing, pass in either an I16 Target-scoped Read/Write FIFO -OR- a Target to Host I16 DMA FIFO. The code parser only looks for the "Write" port and accepts either.

In the debug code, you can then use other code to actually read the FIFO without having to transfer it off the FPGA, allowing for some sanity checks and other useful debugging operations.

-Edit-  This is only ONE example of how to do this. Eliminating Globals and replacing them with "Register" references or "Handshake" references is another thing I love to do. It allows side-by-side comparisons of code versions for saqnity checks. Something which is awful to implement if sharing globals. I've got to organise a presentation on this stuff eventually.

[Pierre_F]

thanks @Intaris for all your advices! I think I will try subvi

@bob_schor, here is the code attached 🙂 (labview 2020)

I'm open to any aditional  advice

[Terry_ALE]

For some, modularity means you can use parts of this code in another project, unit testing, or delegating development to a team.  Are any of these goals of the clutter reduction?

[Pierre_F]

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@Terry_ALE  a écrit :

For some, modularity means you can use parts of this code in another project, unit testing, or delegating development to a team.  Are any of these goals of the clutter reduction?

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I don't have any reason. In NI schools, we use to learn that the code don't have to exceed 1 screen length. As a FPGA newbie, I was afraid to present my code as it is, to VHDL experts, and was scared to face some weird reaction from them. So, I posted it to get your opinion  🙂