Model a dual-port synchronous block RAM with LabVIEW FPGA

[stevensung]

This issue has drawn my attention recently.

I am trying to model a particular design element called "RAMB4_S8_S8" with LabVIEW FPGA module. This element is a dual-port synchronous block RAM that allow simultaneous access from two ports independently to each other. That being said, one port can perform read/write operation to this RAM while at the same time the other port could be able to do that same thing. There are two possible port conflict occasions, though. The first is when two ports are trying to write to the same memory cell. And the other scenario is when one port writes to a memory cell while at the same time the other port reads from it. Other than that everything should be a legitimate operation.

In order to model this I select block memory that is built in my FPGA target. One interface is configured to be read mode and the other is set to write mode. For arbitration option I leave both interfaces to be "Arbitrate if multiple requestors only". Then I got a compilation error when I tried to run my FPGA code for this model in a SCTL. The error message is something like "Multiple objects are requesting access to a resource through a resource interface configured with the "Arbitrate if Multiple Requestors Only" option, which is only supported in the single-cycle Timed Loop if there is only a single requestor per interface".

This error goes away if I replace SCTL with a simple WHILE loop but that is not what I would like to implement. So I am wondering if there is a better solution to this problem, or it is just the limitation of LabVIEW FPGA module.

Thanks.

[JefeL]

Can you post a screenshot of the Single Cycle Timed Loop to give a general sense of how you have it set up?

[stevensung]

Please look at two attached pictures.

This first one, "Single-Cycle Timed Loop", is taken from the overall block diagram that has all modeling codes inside the SCTL. One among these modeling codes is for "Dual-Ported RAM". That is shown in the second picture and is taken from the block diagram that program the logic of this particular FPGA design element. The two occasions of memory reading nodes, are actually what the compiler complains about.

I hope this additional information could be helpful to figure out solution to my problem.

Thanks.

[JefeL]

You indicated that one interface to the memory is a read and the other is a write. This means that you will not be able to perform two read operaitons in the same clock cycle. Your code indicates that you are trying to perform some manual arbitration to model the Xilinx primitive properly but this will not work in a single clock. You can emulate a true dual port memory but you will need to introduce extra clock cycles to perform your own manual arbitration of the conflict cases and perform one read per port. 

[stevensung]

Do you mean that running this modeling in a single-cycle timed loop is still possible if I program it multiple time cycles?

The arbitration is always an issue since the only acceptable option for it inside the SCTL is "Arbitration only if multiple requestors are available". But if I set both read and write interface to this option I will not be able to have either two reading accessing or two writing access to the same block memory simultaneously. And that is unfortunately what I have to model for this dual-ported RAM. Can you say something more about how I could implement this with more than one time cycles and manual arbitration, but inside a SCTL?

Thanks.

[JefeL · Accepted solution]

Yes, you can use some form of pipe line to do the operations you want in sucessive clock cycles but all of the code will be inside a single SCTL. Essentialy, reading the first address and storing it into a register in one cycle and then reading the second address in the second clock cycle. This would provide you two valid memory reads every 2nd clock cycle. I have included a rough snippet to demonstrate the concept. The case selectors are identical with Address A being connected to the memory in the true case, Address B in the false case. Your larger dual port memory model will be intact but it will operate at 1/2 the frequency. 

Take a look at the white paper that provides more detail on the memory constructs:

Data on an FPGA Target (FPGA Module)

The bullet on Block Memory indicates that dual port block memory can only be implemented in a read configuration, which is a ROM. Dual port read/write access will have to be emulated with custom code.

[stevensung]

Thank you Jeff. The trick with pipe line seems like a good workaround to my problem. The only other change that I have to make in order to have it complied correctly, is turning off the arbitration in both interfaces. And then everything is working.