Multiple FPGA FIFO configurations

[Michael_Limerick]

Hello,

I am using one of the NI FPGA products (PXI 7813R). I have been doing some work using the DMA FIFO functions and I have a question regarding the configuration of FIFOs.

I have a FIFO to transfer data from the host to the taget (FIFO_TX) and a FIFO to transfer data between the target and the host (FIFO_RX).

I would like to be able to configure the depth of these FIFO depending on the mode selected.

The mode selection is a boolean, if the control is true then the FIFO depth is 737 if the boolean is false the FIFO depth is 100 (for both FIFO_TX and FIFO_RX).

The attached VIs should show what I am trying to achieve.

I am encountering a problem with this. If the boolena is false the VI executes fine, i.e. I can transfer 100 elements through the FIFO's but then I run the VI again and select the boolean control to true, the VI hangs on the FIFO_read part on the host.

So, is it possible to configure the depths of the FIFOs as I have done? Or can the FIFO only have one depth assigned to it?

I hope I have explained my problem clearly

Thanks for your help and taking the time to read this post.

Regards,

Michael.




Message Edited by Michael_Limerick on 05-18-2008 10:24 AM

[KostasB]

Hi Michael,

I was trying to create a program that would succesfully dynamically modify the FIFO side but I couldn't. The reason is that you are actually allocating memory on the FPGA and it cannot be done dynamically.

The obvious workaround would be to use the minimum FIFO size that would be suitable for both modes (737 in your case), is it something that would be acceptable in your application?

Regards and hope things are going well for you since the last time we met...

KostasB

NI UK Applications Engineering

[Michael_Limerick]

Hi Kostas,

Great to hear from you again : )

I don't think the workaround that you suggested would be suitable for my application. Its great to get feedback though, knowing that a FIFO cannot be dynamically modified is a big help!

I have come up with a different way of doing it. I now have two target VIs and one host VI.

The host VI is attached, so you can have a look what is going on, but basically there is a big case statement and depeding on what the boolean MODE value is, one of the target VIs is selected and downloaded to the target.

One target VI works on the 100 element FIFO and the other target FIFO works with the 737 element FIFO.

It would be most helpful to hear what you think of this approach and its limitations if you think there are any?

Thanks for your help : )

Regards,

Michael.

[KostasB]

Hi Michael,

This solution looks fine.  You could try in the Target VI instead of using a constant as the Number of Iterations in the For Loop (which is either 100 or 737), to use a control and pass this value to the control from the Host VI by using a Write I/O node.

Let me know if that makes sense,

KostasB

NIUK Applications Engineering

[Michael_Limerick]

Hi Kostas,

Yeah, that makes sense. Good suggestion!

I'll give it a try.

Thanks again.

Michael.

[UliB]

Hi Michael,

---

KostasB wrote:

This solution looks fine.  You could try in the Target VI instead of using a constant as the Number of Iterations in the For Loop (which is either 100 or 737), to use a control and pass this value to the control from the Host VI by using a Write I/O node.

---

1) I think KostasB suggestion, to use a control instead of a constant, is better than having the same code twice on the FPGA.

2) I don't understand why you need to read all Elements in your Host VI at once. Use a For Loop in your Host VI to read e.g. 1 Value at a time. This way you can configure your FIFO to a signle depth (e.g. 737 or 1000). In the true case you read 100 Elements and in the false case you read 737 Elements. Also, you don't have to switch between two diffrent FPGA VIs.

I have no insight in your application, so this is just a suggestion, but I hope it helps.

Uli

Message Edited by Uli B. on 05-19-2008 05:03 PM

[Michael_Limerick]

Hi Uli,

Thanks for taking the time to read the post!

That is a very good suggestion for reading one element at a time from the FIFO, thank you very much

I'll try it out,

Regards,

Michael.

[Donovan_B]

Hi Michael,

Just to clarify things, the Configure Depth Invoke Node only configures the depth of the FIFO on the host side only.  In other words, you can make the buffer size larger on the host if you want to process a chunk of data that is a different size than the depth of the FIFO on the FPGA, but Kostas is correct that the FPGA FIFO is allocated when the bitfile is loaded, so this cannot be dynamically changed.  It will always be the original size that you set it to (100 elements).

I think the reason your original VI seems to hang may be that you are trying to read 737 elements at a time with the Invoke Node never timing out.  Since you can only place 100 elements in the FIFO on the FPGA, it could be that you are trying to read a number of elements that is not yet available and when the VI cannot read those elements, it will not time out because of the -1 wired to Timeout parameter of the Invoke Node.  If you change the Timeout value, you may not get all 737 elements, but your VI probably will not hang and you can find out how many elements you are actually receiving.  If it seems like you are not getting all of your samples, you might try to implement something like what Uli suggests and read a smaller number of elements at a time to see if you can get all 737 when you need them.

Message Edited by Donovan B on 05-19-2008 11:17 AM

[FPGA Arch]

The code example could be further simplified to look like this, which will also yield better performance:







Message Edited by FPGA Arch on 05-21-2008 03:13 PM