NI 9216 can only use FPGA mode. why?

[JohanHoltby]

Why do NI9216 only suports FPGA mode and not scan mode?

This seams strange to me.

[GerdW]

Hi Johan,

this module is also supported by DAQmx in cDAQ chassis…

I couldn't find any mention of being not supported by ScanEngine, but I guess it's for the same reason other modules aren't supported by ScanEngine (like NI9853-CAN): maybe NI wanted to keep the ScanEngine "small" and "manageable". Maybe someone from NI might give a better explanation!?

[arevh]

The following compatibility chart shows that NI 9216 module is supported only by cRIO FPGA, besides cDAQ. It is not supported in cRIO Scan mode.

https://www.ni.com/en/support/documentation/supplemental/08/c-series-module-and-compactdaq-compactri...

Thanks,

Arev

CTO | RAFA Solutions

[MichaelAivaliotis]

I asked about this here:

https://forums.ni.com/t5/NI-Blog-ARCHIVED/High-Density-RTD-Measurements-with-the-NI-9216-9226/ba-p/3...

And in a reply there, it was mentioned that NI is planning to support scan mode with the March 2016 release of the CompactRIO device drivers.

My guess is the hardware team was working faster than the software team and they just wanted it out on the market before scan mode was supported.

[JohanHoltby]

To bad I have to deliver next week. 😞

Thank you very much for the information it seams like a reasonable exlplanation.

[JohanHoltby]

Thank you for the link since it will help in the future. Even though it does not explain why as the post below.

[James_McN]

Depending on the long-term need you could use hybrid mode for this module.

Write your own scan-engine like interface with variables and at least when this is released the software changes will be very small.

Obviously this depends on how comfortable you are with this though (if you have to delver tomorrow!)

[JohanHoltby]

Well it's next week wensday so thats 5 days and if I push 14h a day that would be in time no problem. 😉

Kidding aside I think it's the way I have to go. How hard can it be to use som DMA and just push data betwen the FPGA and the RT.