I encountered a technical problem about the FPGA NI 9263. I am using cRIO 9104.
I used 3 channes to output the DAC value from the FPGA NI 9263, I am using C series modules. According to the manual handbook, when I am using 3 channels, the update time of the C series NI 9263 will be 7.5*(10^-6)s, that is the output sampling rate would be 133.3kHz.
However, the FPGA analog output will be connected to the a driver broad with bandwidth 3000Hz (from 0 Hz to 3000Hz, -3dB at 3000Hz and more negative dB for more high frequency), so, the broad may not support so high frequency output from FPGA. May we set the FPGA to make it send out data from FPGA NI 9263 at a lower sampling rate to driver broad? Or adding a device between the FPGA slot and the driver broad is the ONLY way to lower down the sampling rate?
