Hello caz,
I think what you are seeing is a result of several things:
1) The switching rate for the NI 9485 is slower than the 100 Hz you are going for (the
spec sheet says 1 operation per second, however this
additional specifications page
gives graphs showing the actual rates). This would explain why you are
only seeing the last point (especially if you are providing less than
or equal to one seconds worth of data)
2) The rate you input to the timing VI is the maximum rate you are
expecting from your external clock source. So specifying at rate of
100Hz and providing a 20 MHz source does not do any divide down, but
the values are used to configure the buffer sizes.
I believe the way to accomplish what you are trying to do is
demonstrated with the Multi-Function-Synch Dig Read Write With
Counter.vi example. This is in the Example Finder under Hardware Input
and Output»DAQmx»Synchronization»Multi-Function. What this does is use
a counter on the backplane of the cDAQ chassis to provide the sample
clock (i.e. does the divide down). You'll have to get rid of the
digital input part, but thats not too hard...
I do not have the hardware in front of me, but I simulated it and it
ran fine. You just need to make sure your module is in slots 5 or 6 to
access the counters (or I believe you can use just the counter from the
backplane in slots 1-4, e.g. cDAQ1/_ctr0).
I hope this points you in the right direction. Please post back if you have any questions about my explination.
P.S.- I don't know why your image will not work. I tried it too (just to see if it would work for me) and it didn't...
Neal M.
Applications Engineering National Instruments www.ni.com/support
