NI PXIe-7822R Minimum onboard Clock input Frequency

[gowthameie]

Most of the FPGA CARD Minimum input frequency is not mentioned.

I couldn't find the minimum 7822R Minimum onboard Clock input Frequency in PXIe-7822R Datasheet and Specifications.

if anyone know pls share

[l.hovs]

Hi gowthameie, 

By following this article specifications, the 40 MHz Onboard Clock is the default clock in your LabVIEW FPGA project. For achiving the desirable value, which is minimum onboard clock in your case. There is a way to check if your device has opportunity being less then 40MHz.

In your Project explorer window right-click on FPGA target, go to New, FPGA Base Clock and check if your device has ability for minimum frequency.

Regards)

[Terry_ALE]

How slow do you need to go? (ballpark)

[LotsaMotsa]

You can slow the input clock down using a PLL or Clock Manager.  There is a lower limit to these primitives.  What is your application?  There might be a better way to accomplish what you're trying to do.